Information processing apparatus, memory, information processing method, and program

ABSTRACT

A memory control unit and a memory unit is connected to each other by a bus used for transfer of address, data and control signals. The memory control unit outputs a first command including a first predetermined location in the memory unit, to the memory unit. The memory control unit outputs a second command including a second predetermined location in the memory unit, to the memory unit when a predetermined time period has elapsed since the output of the first command.

[0001] This application is based on an application No.2003-104546 filedin Japan, the content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] (1) Field of the Invention

[0003] The present invention relates to an information processingapparatus in which data is written/read to/from a memory, especially toan information processing apparatus in which the same signal lines areshared for transmitting address signals, data signals and controlsignals.

[0004] (2) Description of the Related Art

[0005] A Synchronous Dynamic Random Access Memory (SDRAM) is used for amain storage device in home audio-video equipments such as personalcomputers and digital televisions.

[0006] A CPU included in home audio-video equipments has a cache memorythat achieves a higher transfer rate than an SDRAM. A CPU reads datafrom an SDRAM, and stores the read data in a cache memory before usingit.

[0007] Here, when a cache memory requests data from an SDRAM, itadditionally reads data distributed near the requested data from theSDRAM, and stores therein the additionally read data. Thus, there is ahigher chance that data that will be demanded after the request is alsostored in the cache memory. (see Non-Patent Document 1)

[0008] The requested data and the additionally read data collectivelyform a block.

[0009] An SDRAM allows addresses of wrap around to enabled at a readingto be performed in units of a block.

[0010] Home audio-video equipments also include an LSI, which functionsas a memory control unit. An LSI controls an SDRAM by means of databuses for transmitting data signals, address buses for transmittingaddress signals, and control buses for transmitting control signals(CLK, RAS, CAS, CS, WE, CKE, and DQM) The number of data buses and thenumber of address buses respectively increase in proportion to the bitsof data to be written/read to/from an SDRAM and the bits of an address.

[0011] Recent development of larger capacity memories causes the bits ofdata and the bits of an address to increase, thereby increasing thenumber of data buses and the number of address buses.

[0012] This poses the following problem. More buses requires moreterminals in an LSI to transfer data and addresses, to increase the sizeof the package of an LSI. As a result, the manufacturing cost of an LSIis increased.

[0013] To solve the above-mentioned problem, an information processingapparatus in which an SDRAM is controlled by sharing a same bus whichfunctions as a data bus, an address bus and the like has been developed.(see Patent Document 1)

[0014] However, the information processing apparatus sharing a same busdisclosed in JP2000-267985 can not make use of a wraparound function ofan SDRAM. Accordingly, the information processing apparatus cannotperform information processing with maintaining consistency between datastored in a cache memory and data stored in an SDRAM.

[0015] In light of the above problem, the object of the presentinvention is to provide a useful information processing apparatus whichhas a memory control unit with a smaller number of terminals for signalinput/output and in which information processing is performed withmaintaining consistency between data stored in a cache memory and datastored in a memory unit.

[0016] Patent Document 1: unexamined Japanese patent applicationpublication 2000-267985 Non-Patent Document 1: How Microprocessors Work(Irasuto de yomu microprocessor nyuumon), Gregg Wyant and TuckerHammerstrom, Impress Corporation, 1995, pages 78-79

SUMMARY OF THE INVENTION

[0017] The present invention is an information processing apparatuscomprising a memory unit that has a predetermined burst length and isoperable to transfer block data, using a wraparound method, to/from amemory block that is constituted by a plurality of consecutive memorycells in the memory unit and has a length equal to the predeterminedburst length, and a memory control unit that is connected to the memoryunit by a bus used for both address transfer and data transfer, whereinthe memory control unit includes an output subunit operable to output afirst command and a second command, when the transfer of the block datato/from the memory block starts with transfer of data to/from anintermediate memory cell in the memory block, the intermediate memorycell being a memory cell other than an initial memory cell in the memoryblock, the first command instructing the memory unit to transfer datato/from each of the plurality of memory cells in the memory block,except for a memory cell directly before the intermediate memory cell,the second command being output when a predetermined time has elapsedsince the output of the first command, and instructing the memory unitto transfer data to/from the memory cell directly before theintermediate memory cell in the memory block, and the memory unittransfers the block data in accordance with the first command and thesecond command.

[0018] According to this construction, the number of terminals forsignal input/output in the memory control unit can be reduced, andinformation processing can be performed with maintaining consistencybetween data stored in a cache memory and data stored in the memoryunit.

[0019] Here, the memory unit may be an SDRAM.

[0020] According to this construction, the number of terminals forsignal input/output in the memory control unit can be reduced, andinformation processing can be performed with maintaining consistencybetween data stored in a cache memory and data stored in the SDRAM.

[0021] Here, the first command may include a writing instruction and anaddress indicating the memory cell directly before the intermediatememory cell, the second command may include a writing instruction and anaddress indicating a memory cell two memory cells before theintermediate memory cell.

[0022] According to this construction, the number of terminals forsignal input/output in the memory control unit can be reduced, data iswritten into the memory unit in a wraparound method, and informationprocessing can be performed with maintaining consistency between datastored in a cache memory and data stored in the memory unit.

[0023] Here, the first command may include a reading instruction and anaddress indicating the intermediate memory cell, the second command mayinclude a reading instruction and an address indicating the memory celldirectly before the intermediate memory cell.

[0024] According to this construction, the number of terminals forsignal input/output in the memory control unit can be reduced, data isread from the memory unit in a wraparound method, and informationprocessing can be performed with maintaining consistency between datastored in a cache memory and data stored in the memory unit.

[0025] Here, the present invention may be an information processingapparatus comprising a memory unit that has a burst length larger than ablock length of a memory block and is operable to transfer block datato/from the memory block constituted by a plurality of consecutivememory cells in the memory unit, a memory control unit that is connectedto the memory unit by a bus used for both address transfer and datatransfer, a cache unit operable to request the memory control unit totransfer the block data to/from the memory unit, a writing unit operableto (i) receive, from the cache unit, an address indicating anintermediate memory cell in the memory block, the block data, and awriting request, the intermediate memory cell being a memory cell otherthan an initial memory cell in the memory block, and (ii) store datainto each of the plurality of memory cells in the memory block in thememory unit in an order of from the initial memory cell to a finalmemory cell in the memory block, and a reading unit operable to (a)receive, from the cache unit, the address indicating the intermediatememory cell in the memory block, and a reading request, (b) read datafrom each of the plurality of memory cells in the memory block in thememory unit in an order of from the initial memory cell to the finalmemory cell, and (c) send the read data to the cache unit, using awraparound method, starting with data read from the intermediate memorycell and ending with data read from a memory cell directly before theintermediate memory cell.

[0026] According to this construction, the number of terminals forsignal input/output in the memory control unit can be reduced, andinformation processing can be performed with maintaining consistencybetween data stored in a cache memory and data stored in the memoryunit.

[0027] Here, the memory unit may be an SDRAM, and the informationprocessing apparatus may include a writing unit operable to (i) receive,from the cache unit, an address indicating an intermediate memory cellin the memory block, the block data, and a writing request, theintermediate memory cell being a memory cell other than an initialmemory cell in the memory block, and (ii) store data into each of theplurality of memory cells in the memory block in the memory unit in anorder of from the initial memory cell to a final memory cell in thememory block, and a reading unit operable to (a) receive, from the cacheunit, the address indicating the intermediate memory cell in the memoryblock, and a reading request, (b) read data from each of the pluralityof memory cells in the memory block in the memory unit in an order offrom the initial memory cell to the final memory cell, and (c) send theread data to the cache unit, using a wraparound method, starting withdata read from the intermediate memory cell and ending with data readfrom a memory cell directly before the intermediate memory cell.

[0028] According to this construction, the number of terminals forsignal input/output in the memory control unit can be reduced, andinformation processing can be performed with maintaining consistencybetween data stored in a cache memory and data stored in the SDRAM.

[0029] Here, the present invention may be a memory operable to storedata in accordance with signals input thereto, the signals including acontrol signal such as a clock, an address signal, and a data signal,the memory comprising a transmission unit operable to transmit thesignals, a detection unit operable to detect an edge of the clock, amemory cell group that is constituted by a plurality of memory cellseach of which has an assigned address, an address storing unit operableto (i) retrieve an address signal when the detection unit detects anedge of the clock at a predetermined timing, and (ii) store therein theretrieved address signal as a writing address, an address addition unitoperable to increment the writing address, after an edge is detectedsubsequent to the detection of the edge at the predetermined timing, butbefore a next edge is detected, a data storing unit operable to retrievea data signal every time the detection unit detects an edge of theclock, after the detection unit detects the edge at the predeterminedtiming, and a control unit operable to perform control so that, everytime the data storing unit retrieves a data signal, the retrieved datasignal is written into a memory cell indicated by the writing addressstored in the address storing unit.

[0030] According to this construction, the memory control unit does notneed to perform an address decrement operation, and the number ofterminals for signal input/output in the memory control unit can bereduced.

[0031] Here, the transmission unit may include one signal input/outputterminal for two of the address signal, the data signal, and the controlsignal, one of the two signals being input to the signal input/outputterminal at a time, and a signal line which is connected to two unitsselected from (i) the address storing unit that stores the writingaddress indicating the memory cell to which the data signal is to bewritten, (ii) the data storing unit that stores the data signal that isto be written to the memory cell, and (iii) the control unit thatcontrols the writing of the data signal, so as that the selected twounits correspond to the two signals input to the signal input/outputterminal.

[0032] According to this construction, the number of terminals forsignal input/output in the memory control unit and the memory can bereduced, and information processing can be performed with maintainingconsistency between data stored in a cache memory and data stored in thememory.

[0033] Here, the memory may be an SDRAM, and may include a transmissionunit operable to transmit the signals, a detection unit operable todetect an edge of the clock, a memory cell group that is constituted bya plurality of memory cells each of which has an assigned address, anaddress storing unit operable to (i) retrieve an address signal when thedetection unit detects an edge of the clock at a predetermined timing,and (ii) store therein the retrieved address signal as a writingaddress, an address addition unit operable to increment the writingaddress, after an edge is detected subsequent to the detection of theedge at the predetermined timing, but before a next edge is detected, adata storing unit operable to retrieve a data signal every time thedetection unit detects an edge of the clock, after the detection unitdetects the edge at the predetermined timing, and a control unitoperable to perform control so that, every time the data storing unitretrieves a data signal, the retrieved data signal is written into amemory cell indicated by the writing address stored in the addressstoring unit.

[0034] According to this construction, the number of terminals forsignal input/output in the memory control unit and the SDRAM can bereduced, and information processing can be performed with maintainingconsistency between data stored in a cache memory and data stored in theSDRAM.

[0035] Here, the present invention may be an information processingmethod for transferring data to/from a memory by means of a bus used forboth address transfer and data transfer, the memory operating inaccordance with a command, having a predetermined burst length, andtransferring block data, by using a wraparound method, to/from a memoryblock that is constituted by a plurality of memory cells in the memoryand has a length equal to the predetermined burst length, theinformation processing method comprising a first output step of, whenthe transfer of the block data to/from the memory block starts withtransfer of data to/from an intermediate memory cell in the memoryblock, the intermediate memory cell being a memory cell other than aninitial memory cell in the memory block, outputting a first command toinstruct the memory to transfer data to/from each of the plurality ofmemory cells in the memory block, except for a memory cell directlybefore the intermediate memory cell, and a second output step of, when apredetermined time has elapsed since the output of the first command,outputting a second command to instruct the memory to transfer datato/from the memory cell directly before the intermediate memory cell inthe memory block.

[0036] According to this construction, the number of terminals forsignal input/output can be reduced, and information processing can beperformed with maintaining consistency between data stored in a cachememory and data stored in the memory.

[0037] Here, the present invention may be a program used in aninformation processing apparatus that transfers data to/from a memory bymeans of a bus used for both address transfer and data transfer, thememory operating in accordance with a command, having a predeterminedburst length, and transfer block data, by using a wraparound method,to/from a memory block that is constituted by a plurality of memorycells in the memory and has a length equal to the predetermined burstlength, the program comprising a first output step of, when the transferof the block data to/from the memory block starts with transfer of datato/from an intermediate memory cell in the memory block, theintermediate memory cell being a memory cell other than an initialmemory cell in the memory block, outputting a first command to instructthe memory to transfer data to/from each of the plurality of memorycells in the memory block, except for a memory cell directly before theintermediate memory cell, and a second output step of, when apredetermined time has elapsed since the output of the first command,outputting a second command to instruct the memory to transfer datato/from the memory cell directly before the intermediate memory cell inthe memory block.

[0038] According to this construction, the number of terminals forsignal input/output can be reduced, and information processing can beperformed with maintaining consistency between data stored in a cachememory and data stored in the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] These and the other objects, advantages and features of theinvention will become apparent from the following description thereoftaken in conjunction with the accompanying drawings which illustrate aspecific embodiment of the invention.

[0040] In the drawings:

[0041]FIG. 1 illustrates a construction of an information processingapparatus of the present invention;

[0042]FIG. 2 illustrates a construction of writing data a memory controlunit writes into an SDRAM in response to a request from a CPU;

[0043]FIG. 3 illustrates a part of a memory area for storing data in theSDRAM;

[0044]FIG. 4 is a block diagram illustrating a construction of thememory control unit;

[0045]FIG. 5 is a timing diagram for signals transmitted between thememory control unit and the SDRAM when the memory control unit readsdata from the SDRAM;

[0046]FIG. 6 is a timing diagram for signals transmitted between thememory control unit and the SDRAM when the memory control unit writesdata into the SDRAM;

[0047]FIG. 7 illustrates a construction of a memory control unit;

[0048]FIG. 8 is a timing diagram for signals transmitted between thememory control unit and the SDRAM when the memory control unit readsdata from the SDRAM;

[0049]FIG. 9 is a timing diagram for signals transmitted between thememory control unit and the SDRAM when the memory control unit writesdata into the SDRAM;

[0050]FIG. 10 illustrates a construction of an information processingapparatus using a memory unit;

[0051]FIG. 11 is a block diagram illustrating a construction of thememory unit;

[0052]FIG. 12 briefly illustrates a construction of a memory cell array;

[0053]FIG. 13 is a timing diagram for signals transmitted between thememory control unit and the memory unit when the memory control unitwrites data into the memory unit; and

[0054]FIG. 14 is a timing diagram for signals transmitted between thememory control unit and the memory unit when the memory control unitreads data from the memory unit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] 1. First Embodiment

[0056] 1.1 Construction

[0057]FIG. 1 shows a construction of an information processing apparatus1 relating to a first embodiment of the present invention.

[0058] A memory control unit 10 is electrically connected to a CPU 30 bya bus.

[0059] Concretely speaking, the memory control unit 10 is an LSI tocontrol an SDRAM 20.

[0060] As shown in FIG. 1, the memory control unit 10 is electricallyconnected to the SDRAM 20 by signal lines which transmits one or twokinds of signals selected from address signals, data signals and controlsignals.

[0061] The memory control unit 10 transmits/receives a 14-bit addressto/from the SDRAM 20. Such a 14-bit address from A13 to A0 is shown asA(13:0) in FIG. 1.

[0062] Similarly, the memory control unit 10 transmits/receives 16-bitdata to/from the SDRAM 20. Such 16-bit data from D15 to D0 is shown asD(13:0), D(14), and D(15).

[0063] The memory control unit 10 transmits/receives data to/from theSDRAM 20 in units of 16 bits, which is equivalent to one word.

[0064] Control signals include RAS, CAS, CKE, WE, CS, DQM and CLK. Thesesignals are defined by the control specification of an SDRAM, andtherefore not explained in detail.

[0065] The SDRAM 20 has a plurality of memory cells each of which storesdata of one word.

[0066] Each memory cell is identified by a pair of a 14-bit row addressand a 14-bit column address.

[0067] In the first embodiment, it is assumed that the memory controlunit 10 writes/reads data to/from memory cells that have a row addressof 0.

[0068] To generate commands defined by the SDRAM control specification,the memory control unit 10 holds RAS, CAS, CKE, WE, CS, DQM and CLK highor low, in synchronization with CLK, based on the control specification.

[0069] For example, the memory control unit 10 holds CS, CAS and WE low,and RAS high, to generate a write command that instructs the SDRAM 20 toperform a write operation.

[0070] According to the first embodiment, the memory control unit 10uses an active command, a read command, a write command, and a burststop command, which are defined by the SDRAM control specification, inorder to control the SDRAM 20.

[0071] The CPU 30 requests the memory control unit 10 to perform dataread and write operations in units of block data constituted by fourwords.

[0072] The memory control unit 10 requests the SDRAM 20 totransmit/receive data in units of block data constituted by four words,in accordance with an instruction from the CPU 30.

[0073]FIG. 2 shows a construction of writing data which the memorycontrol unit 10 writes into the SDRAM 20 in response to a request fromthe CPU 30.

[0074] Writing data is block data which includes writing data 202,writing data 203, writing data 204, and writing data 201. The writingdata 202, 203, 204 and 201 are respectively equivalent to one word.

[0075]FIG. 3 shows a part of a memory area in the SDRAM 20 for storingdata.

[0076] Here, it is assumed that a row address of the memory area in FIG.3 is zero.

[0077] A memory area is constituted by a plurality of memory cells eachof which stores data of one word. Each memory cell has an assignedcolumn address, which is one of 0x0000 to 0x3FFF.

[0078] A memory block 305 is constituted by memory cells 301 to 304.Column addresses from 0x0A00 to 0x0A03 are respectively allocated to thememory cells 301 to 304.

[0079] Here, the above numerical values starting with 0x are hexadecimalnumerals. For example, 0x0A00 is 0A00 in hexadecimal.

[0080] In a memory block, a memory cell with the smallest column addressand a memory cell with the largest column address are respectivelycalled a block start cell and a block end cell.

[0081] An address for a block start cell is called a block startaddress, and an address for a block end cell is a block end address.

[0082] The smallest digit of a column address in hexadecimal of a blockstart address is divisible by four, such as 0x0A00 and 0x0A04.

[0083] In the memory block 305, the block start cell is the memory cell301, and the block end cell is the memory cell 304.

[0084] It is assumed that the SDRAM 20 operates in a burst transfer modeand has a burst length set to four, which is equal to the number ofwords in a memory block.

[0085] The SDRAM 20 has a CAS Latency of 2.

[0086] The SDRAM 20 has a wraparound function, which enables datainput/output to/from a block start cell is performed after datainput/output to/from a block end cell.

[0087] For instance, the SDRAM 20 receives an active command and a rowaddress from the memory control unit 10. Then, the SDRAM 20 receives awrite command, a column address, which is the column address of thememory cell 302 here, and the writing data 202, the writing data 203,the writing data 204, and the writing data 201. Here, the SDRAM 20writes the writing data 202 into the memory cell 302, the writing data203 into the memory cell 303, the writing data 204 into the memory cell304, i.e. the block end cell. After this, the SDRAM 20 writes thewriting data 201 into the memory cell 301, i.e. the block start cellusing a wraparound method.

[0088] 1.1.1. Memory Control Unit 10

[0089]FIG. 4 is a block diagram illustrating a construction of thememory control unit 10.

[0090] (CAS Latency Storing Unit 101)

[0091] A CAS Latency storing unit 101 prestores CAS Latency relating tothe specification of the SDRAM 20.

[0092] The CAS Latency storing unit 101 stores a numerical value of 2 asCAS Latency of the SDRAM 20.

[0093] (Block Length Storing Unit 102)

[0094] A block length storing unit 102 prestores a burst length definedin the SDRAM 20, as a block length.

[0095] The block length storing unit 102 stores a numerical value of 4,which is a burst length defined by the SDRAM 20, as a block length.

[0096] (Clock Generation Unit 103)

[0097] A clock generation unit 103 generates a clock signal to besupplied to the SDRAM 20.

[0098] The SDRAM 20 examines whether an input signal is held high or lowon the rising edge of a clock signal, and performs an operationcorresponding to the result of the examination.

[0099] (Address Buffer Unit 104)

[0100] An address buffer unit 104 receives a start row address and astart column address from the CPU 30, and stores them therein. A startrow address and a start column addresses are a pair of a row address anda column address indicating a memory cell from which data input/outputstarts.

[0101] The address buffer unit 104 sends a start column address to afirst column address generation unit 105 and a second column addressgeneration unit 106.

[0102] (First Column Address Generation Unit 105)

[0103] If a start column address received from the address buffer unit104 is a block start address, the first column address generation unit105 sets a block end address as a first column address. If not, thefirst column address generation unit 105 subtracts one from a startcolumn address received from the address buffer unit 104, and sets theresult address of the subtraction as a first column address.

[0104] (Second Column Address Generation Unit 106)

[0105] If a first column address is a block start address, the secondcolumn address generation unit 106 sets a block end address as a secondcolumn address. If not, the second column address generation unit 106subtracts one from a first column address, and set the result address ofthe subtraction as a second column address.

[0106] (Writing Data Buffer Unit 107)

[0107] A writing data buffer unit 107 stores writing data received fromthe CPU 30.

[0108] (Reading Data Buffer Unit 108)

[0109] A reading data buffer unit 108 stores reading data received fromthe SDRAM 20.

[0110] (Selector 109)

[0111] A selector 109 selects a signal group to be output, out of aplurality of signal groups that are input thereto, in accordance with aselection instruction received from a control unit 110 (mentionedlater).

[0112] A selection instruction is expressed by a value selected from 1to 5.

[0113] Receiving a selection instruction of 1, the selector 109 connectsa bus 131 and a bus 132 with a bus 122. The bus 122 is composed of 16signal lines, the bus 131 of two signal lines, and the bus 132 of 14signal lines.

[0114] Receiving a selection instruction of 2, the selector 109 connectsthe bus 131 and a bus 133 with the bus 122.

[0115] Receiving a selection instruction of 3, the selector 109 connectsthe bus 131 and a bus 134 with the bus 122.

[0116] Receiving a selection instruction of 4, the selector 109 connectsa bus 135 with the bus 122.

[0117] Receiving a selection instruction of 5, the selector 109 connectsa bus 136 with the bus 122.

[0118] (Control Unit 110)

[0119] The control unit 110 receives a writing request or a readingrequest from the CPU 30. A writing request instructs data input to theSDRAM 20, and a reading request instructs data output from the SDRAM 20.

[0120] The control unit 110 reads/writes data from/to the SDRAM 20,according to a request received from the CPU 30.

[0121] The control unit 110 generates an active command, a writecommand, a read command, and a burst stop command, using controlsignals, to send the commands to the SDRAM 20.

[0122] In addition, the control unit 110 sends a selection instructionto the selector 109 so as that a signal group to be transmitted throughthe bus 122 is selected.

[0123] (Bus 121)

[0124] A bus 121 is a signal line group composed of five signal lines totransmit signals of CS, WE, CKE, DQM and CLK respectively.

[0125] (Bus 122)

[0126] The bus 122 is composed of 16 signal lines.

[0127] (Bus 131)

[0128] The bus 131 is a signal line group composed of two signal linesto transmit signals of RAS and CAS respectively.

[0129] (Bus 132)

[0130] The bus 132 is a signal line group composed of 14 signal lines totransmit, in parallel, one of a 14-bit row address and a 14-bit columnaddress output from the address buffer unit 104.

[0131] (Bus 133)

[0132] The bus 133 is a signal line group composed of 14 signal lines totransmit, in parallel, a 14-bit first column address output columnaddress of 0x0A01 are input to the memory control unit 10.

[0133] The control unit 110 receives the reading request from the CPU30.

[0134] The address buffer unit 104 receives and stores therein the startrow address and the start column address.

[0135] The address buffer unit 104 sends the start column address to thefirst column address generation unit 105 and the second column addressgeneration unit 106.

[0136] The first column address generation unit 105 generates a firstcolumn address of 0x0A00 based on the received start column address of0x0A01.

[0137] The second column address generation unit 106 generates a secondcolumn address of 0x0A03 based on the received start column address of0x0A01.

[0138] Here, the second column address generation unit 105 may notgenerate a second column address to perform a reading operation, as thememory control unit 10 does not require a second column address to readdata from the SDRAM 20.

[0139] (T01, Between T01 and T02)

[0140] The control unit 110 sends a selection instruction of 1 to theselector 109.

[0141] The selector 109 connects the buses 131 and 132 with the bus 122in accordance with the selection instruction.

[0142] The address buffer unit 104 outputs the start row address to thebus 132 in accordance with an instruction from the control unit 110.

[0143] The control unit 110 holds CKE and DQM high.

[0144] The control unit 110 holds CAS and WE high, and CS and RAS low,to generate an active command.

[0145] (T02, Between T02 and T03)

[0146] At the time T02, the SDRAM 20 receives the active command and thestart row address.

[0147] (T03, Between T03 and T05)

[0148] At the time T03, the control unit 110 holds CS high.

[0149] (T05, Between T05 and T06)

[0150] The address buffer unit 104 outputs the start column address tothe bus 132 in accordance with an instruction from the control unit 110.

[0151] At the time T05, the control unit 110 holds DQM low.

[0152] At the time T05, the control unit 110 holds CS and CAS low, andRAS and WE high, to generate a read command.

[0153] (T06, Between T06 and T07)

[0154] At the time T06, the SDRAM 20 receives the read command and thestart column address.

[0155] (T07)

[0156] The control unit 110 holds CS and CAS high.

[0157] (Between T07 and T09, T09)

[0158] The control unit 110 sends a selection instruction of 5 to theselector 109.

[0159] The selector 109 connects the bus 136 with the bus 122 inaccordance with the selection instruction.

[0160] (Between T09 and T11)

[0161] The SDRAM 20 outputs reading data 312 stored in the memory cell302, which is identified by the start column address, to the bus 122.

[0162] The reading data buffer unit 108 receives the reading data 312,and sends it to the CPU 30.

[0163] (T11)

[0164] The control unit 110 holds DQM high.

[0165] (Between T11 and T13)

[0166] The SDRAM 20 outputs reading data 313 stored in the memory cell303, to the bus 122.

[0167] At the time T12, the reading data buffer unit 108 receives thereading data 313, and sends it to the CPU 30.

[0168] As DQM is held high at the time T12, the SDRAM 20 judges that itdoes not need to output data after the time T16. This is because CASLatency is 2 and the time T16 corresponds to the second rising edge ofthe clock signal after the time T12.

[0169] (T13, Between T13 and T15)

[0170] The SDRAM 20 outputs reading data 314 stored in the memory cell304 to the bus 122.

[0171] At the time T14, the reading data buffer unit 108 receives thereading data 314, and sends it to the CPU 30.

[0172] (T15, Between T15 and T16)

[0173] The control unit 110 sends a selection instruction of 2 to theselector 109.

[0174] The selector 109 connects the buses 131 and 133 with the bus 122.

[0175] The control unit 110 holds DQM low.

[0176] The control unit 110 holds CS and CAS low, and RAS and WE high,to generate a read command.

[0177] The first column address generation unit 105 outputs the firstcolumn address to the bus 133 in accordance with an instruction from thecontrol unit 110.

[0178] (T16, Between T16 and T17)

[0179] At the time T16, the SDRAM 20 receives the read command and thefirst column address.

[0180] As DQM is held low at the time T16, the SDRAM 20 judges that itneeds to output data after the time T20. This is because CAS Latency is2 and the time T20 corresponds to the second rising edge of the clocksignal after the time T16.

[0181] (T17)

[0182] The control unit 110 holds DQM high.

[0183] The control unit 110 holds CS and WE low, and RAS and CAS high,to generate a burst stop command.

[0184] (Between T17 and T19)

[0185] At the time T18, the SDRAM 20 receives the burst stop command.

[0186] The control unit 110 maintains control signals as they are.

[0187] The control unit 110 sends a selection instruction of 5 to theselector 109.

[0188] The selector 109 connects the bus 136 with the bus 122.

[0189] (T19, Between T19 and T20, T20)

[0190] The SDRAM 20 outputs, to the bus 122, reading data 311 stored inthe memory cell 301, which has been selected using a wraparound method.

[0191] At the time T20, the reading data buffer unit 108 receives thereading data 311, and sends it to the CPU 30.

[0192] 1.2.2. Write Operation

[0193]FIG. 6 is a timing diagram for signals transmitted between thememory control unit 10 and the SDRAM 20 when the memory control unit 10writes data into the SDRAM 20.

[0194] (Before T31)

[0195] The CPU 30 sends a writing request, a start row address and astart column address for identifying a memory cell from which datawriting starts, and the writing data 202, 203, 204, and 201, which is tobe written into the SDRAM 20, to the memory control unit 10.

[0196] Here, it is assumed that a start row address of 0 and a startcolumn address of 0x0A01 are input to the memory control unit 10.

[0197] The control unit 110 receives the writing request from the CPU30.

[0198] The address buffer unit 104 receives and stores therein the startrow address and the start column address.

[0199] The address buffer unit 104 sends the start column address to thefirst column address generation unit 105 and the second column addressgeneration unit 106.

[0200] The first column address generation unit 105 generates a firstcolumn address of 0x0A00 based on the received start column address.

[0201] The second column address generation unit 106 generates a secondcolumn address of 0x0A03 based on the received start column address.

[0202] (T31, Between T31 and T32)

[0203] The control unit 110 sends a selection instruction of 1 to theselector 109.

[0204] The selector 109 receives the selection instruction, and connectsthe buses 131 and 132 with the bus 122.

[0205] The address buffer unit 104 outputs the start row address to thebus 132 in accordance with an instruction from the control unit 110.

[0206] The control unit 110 holds CKE and DQM high.

[0207] The control unit 110 holds CAS and WE high, and CS and RAS low,to generate an active command.

[0208] (T32, Between T32 and T33)

[0209] At the time T32, the SDRAM 20 receives the active command.

[0210] (T33)

[0211] The control unit 110 holds CS high.

[0212] (Between T33 and T35)

[0213] The control unit 110 sends a selection instruction of 2 to theselector 109.

[0214] The selector 109 connects the buses 131 and 133 with the bus 122.

[0215] (T35, Between T35 and T36)

[0216] The first column address generation unit 105 outputs the firstcolumn address to the bus 133 in response to an instruction from thecontrol unit 110.

[0217] At the time T35, the control unit 110 holds DQM high.

[0218] At the time T35, the control unit 110 holds CS, CAS and WE low,and RAS high, to generate a write command.

[0219] (T36, Between T36 and T37)

[0220] At the time T36, the SDRAM 20 receives the write command and thefirst column address.

[0221] As DQM is held high at the time T36, the SDRAM 20 judges thatsignals D(15:0) are invalid. Therefore, the SDRAM 20 does not write datainto the memory cell 301, which is indicated by the first columnaddress.

[0222] Between the time T36 and the time T37, the control unit 110 sendsa selection instruction of 4 to the selector 109.

[0223] The selector 109 connects the bus 135 with the bus 122.

[0224] (T37)

[0225] The control unit 110 holds CS and CAS high.

[0226] The control unit 110 holds DQM low.

[0227] (Between T37 and T39)

[0228] The writing data buffer unit 107 outputs the writing data 202 tothe bus 135 in accordance with an instruction from the control unit 110.

[0229] At the time T38, the SDRAM 20 writes the writing data 202 intothe memory cell 302, which has an address next to that of the memorycell 301.

[0230] (T39, Between T39 and T41)

[0231] The writing data buffer unit 107 outputs the writing data 203 tothe bus 135 in accordance with an instruction from the control unit 110.

[0232] At the time T40, the SDRAM 20 writes the writing data 203 intothe memory cell 303, which has an address next to that of the memorycell 302.

[0233] (T41, Between T41 and T43)

[0234] The writing data buffer unit 107 sends the writing data 204 tothe bus 135 in accordance with an instruction from the control unit 110.

[0235] At the time T42, the SDRAM 20 writes the writing data 204 intothe memory cell 304 which has an address next to that of the memory cell303.

[0236] (T43)

[0237] The control unit holds DQM high.

[0238] The control unit 110 holds CS, CAS and WE low, and RAS and high,to generate a write command.

[0239] (Between T43 and T44)

[0240] The control unit 110 sends a selection instruction of 3 to theselector 109.

[0241] The selector 109 connects the buses 131 and 134 with the bus 122.

[0242] The second column address generation unit 106 outputs the secondcolumn address to the bus 134 in accordance with an instruction from thecontrol unit 110.

[0243] (T44, Between T44 and T45)

[0244] At the time T44, the SDRAM 20 receives the write command and thesecond column address.

[0245] As DQM is held high at the time T44, the SDRAM 20 does not writedata into the memory cell 304 which is identified by the second columnaddress.

[0246] (T45)

[0247] The control unit 110 holds CS high.

[0248] The control unit 110 holds DQM low.

[0249] (Between T45 and T46)

[0250] The control unit 110 sends a selection instruction of 4 to theselector 109.

[0251] The selector 109 connects the bus 135 with the bus 122.

[0252] The writing data buffer unit 107 outputs the writing data 201 tothe bus 135 in accordance with an instruction from the control unit 110.

[0253] (T46, Between T46 and T47)

[0254] At the time T46, the SDRAM 20 writes the writing data 201 intothe memory cell 301. The address of the memory cell 301 is next to thatof the memory cell 304 in a wraparound method.

[0255] (T47)

[0256] The control unit 110 holds DQM high.

[0257] The control unit 110 holds CS and WE low, and RAS and CAS high,to generate a burst stop command.

[0258] (Between T47 and T48, T48)

[0259] At the time T48, the SDRAM 20 receives the burst stop command.

[0260] 2. Second Embodiment

[0261] 2.1. Construction

[0262] An information processing apparatus 2 relating to a secondembodiment is the same as the information processing apparatus 1 exceptfor a memory control unit 50, which replaces the memory control unit 10shown in FIG. 1.

[0263] The CPU 30 sends the same data writing and reading requests tothe memory control unit 50 as the data writing and reading requests sentfrom the CPU 30 to the memory control unit 10 in the first embodiment.

[0264] A burst length for the SDRAM 20 is set to a value equal to thesmallest possible length which allows writing and reading of data havinga size equal to (a block length+1).

[0265] The SDRAM 20 defines a burst length of 2, 4 or 8, which is then-th power of 2.

[0266] As a block length is set to four, a burst length in the SDRAM 20is set to eight in the second embodiment.

[0267] 2.1.1. Memory Control Unit 50

[0268]FIG. 7 shows a construction of the memory control unit 50.

[0269] (Address Buffer Unit 501)

[0270] An address buffer unit 501 receives a start row address and astart column address from the CPU 30, and stores them. A pair of a startrow address and a start column address indicate a memory cell from whichdata input/output starts.

[0271] The address buffer unit 501 sends a start column address to anoffset control unit 502 (described later).

[0272] (Offset Control Unit 502)

[0273] The offset control unit 502 receives a start column address fromthe address buffer unit 501.

[0274] The offset control unit 502 generates either a writing columnaddress or a reading column address based on a start column address fromthe address buffer unit 501.

[0275] More specifically, when the CPU 30 sends a writing request to thememory control unit 50, the offset control unit 502 selects a block endaddress of a memory block to which a memory cell indicated by a startcolumn address belongs, as a writing column address.

[0276] When the CPU 30 sends a reading request to the memory controlunit 50, the offset control unit 502 selects a block start address ofthe memory block as a reading column address.

[0277] The offset control unit 502 calculates an offset value, which isa difference between a start column address and a block start address.

[0278] The calculation of an offset value is explained with reference tothe memory block 305 in FIG. 3. If a start column address is 0x0A01, ablock start address is 0x0A00, which is the column address of the memorycell 301. Accordingly, an offset value is 1.

[0279] (Writing Data Buffer Unit 503)

[0280] A writing data buffer unit 503 stores therein writing data inputfrom the CPU 30.

[0281] When sending a data writing request, the CPU 30 sends the writingdata 202, the writing data 203, the writing data 204, and the writingdata 201 to the writing data buffer unit 503 in the stated order.

[0282] The writing data buffer unit 503 outputs the writing data 201,the writing data 202, the writing data 203, and the writing data 204 inthis order to the SDRAM 20 through a bus 533 (mentioned later), inresponse to an instruction from a control unit 506 (mentioned later).Here, the writing data 201 corresponds to a block start address.

[0283] (Reading Data Buffer Unit 504)

[0284] A reading data buffer unit 504 stores therein reading data inputfrom the SDRAM 20.

[0285] The SDRAM 20 outputs the reading data 311, the reading data 312,the reading data 313, and the reading data 314, in the stated order, tothe reading data buffer unit 504.

[0286] The reading data buffer unit 504 receives the reading data 311,the reading data 312, the reading data 313, and the reading data 314, inthis order, from the SDRAM 20.

[0287] The reading data buffer unit 504 does not output the reading fromthe first column address generation unit 105.

[0288] (Bus 134)

[0289] The bus 134 is a signal line group composed of 14 signal lines totransmit, in parallel, a 14-bit second column address output from thesecond column address generation unit 106.

[0290] (Bus 135)

[0291] The bus 135 is a signal line group composed of 16 signal lines totransmit, in parallel, 16-bit writing data output from the writing databuffer unit 107.

[0292] (Bus 136)

[0293] The bus 136 is a signal line group composed of 16 signal lines totransmit, in parallel, 16-bit reading data output from the SDRAM 20 tothe reading data buffer unit 108.

[0294] 1.2. Operation

[0295] 1.2.1. Read Operation

[0296]FIG. 5 is a timing diagram for signals transmitted between thememory control unit 10 and the SDRAM 20 when the memory control unit 10reads data from the SDRAM 20.

[0297] In FIG. 5, reference marks T01 to T20 each indicate the timing atwhich a rising edge or a falling edge of CLK is generated.

[0298] (Before T01)

[0299] The CPU 30 outputs a reading request, and a start row address anda start column address for identifying a memory cell from which datareading starts, to the memory control unit 10.

[0300] Here, it is assumed that a start row address of 0 and a startdata 311 to 314 one by one to the CPU 30 immediately after receivingeach of them from the SDRAM 20. Instead, the reading data buffer unit504 outputs the reading data 311 to 314 from the SDRAM 20 to the CPU 30only after it receives all of the reading data 311 to 314 correspondingto one block.

[0301] If the reading data buffer unit 504 receives reading data 311 to314 corresponding to one block from the SDRAM 20, it outputs the readingdata 311 to 314 in response to an instruction from the control unit 506in the following manner 0. A start column address is regenerated byadding an offset value to a block start address. Then, the reading databuffer unit 504 first outputs, to the bus 533, the reading data 312corresponding to the start column address, then in the order of thereading data 313, the reading data 314, and the reading data 311.

[0302] (Selector 505)

[0303] A selector 505 selects a signal group to be output, out of aplurality of signal groups input thereto, based on a selectioninstruction received from the control unit 506.

[0304] A selection instruction is one of the values from 1 to 4.

[0305] Receiving a selection instruction of 1, the selector 505 connectsthe bus 131 and a bus 531 with the bus 122. The bus 131 is composed oftwo signal lines, the bus 531 of 14 signal lines, and the bus 122 of 16signal lines.

[0306] Receiving a selection instruction of 2, the selector 505 connectsthe bus 131 and a bus 532 with the bus 122. The bus 131 is composed oftwo signal lines, the bus 532 of 14 signal lines, and the bus 122 of 16signal lines.

[0307] Receiving a selection instruction of 3, the selector 505 connectsthe bus 533 with the bus 122.

[0308] Receiving a selection instruction of 4, the selector 505 connectsa bus 534 with the bus 122.

[0309] (Control Unit 506)

[0310] The control unit 506 receives, from the CPU 30, a writing requestto input data into the SDRAM 20 and a reading request to obtain datafrom the SDRAM 20.

[0311] The control unit 506 writes/reads data to/from the SDRAM 20,based on a request received from the CPU 30.

[0312] The control unit 506 generates an active command, a writecommand, a read command, and a burst stop command using control signals,and sends them to the SDRAM 20.

[0313] Such active, write, read, and burst stop commands are defined bythe control specifications of the SDRAM 20.

[0314] The control unit 506 sends a selection instruction to theselector 505 so as to select a signal group to be transmitted throughthe bus 122.

[0315] When writing data into the SDRAM 20, the control unit 506requires the writing data buffer unit 503 to send writing data to theSDRAM 20, starting from data that should be written into a start memorycell of a block.

[0316] When reading data from the SDRAM 20, the control unit 506requires the reading data buffer unit 504 to send reading data to theCPU 30, starting with data corresponding to a start column address.

[0317] (Bus 531)

[0318] The bus 531 is a signal line group composed of 14 signal lines totransmit, in parallel, a 14-bit block end address output from theaddress buffer unit 501.

[0319] (Bus 532)

[0320] The bus 532 is a signal line group composed of 14 signal lines totransmit, in parallel, a 14-bit block start address output from theoffset control unit 502.

[0321] (Bus 533)

[0322] The bus 533 is a signal line group composed of 16 signal lines totransmit, in parallel, 16-bit writing data output from the writing databuffer unit 503.

[0323] (Bus 534)

[0324] The bus 534 is a signal line group composed of 16 signal lines totransmit, in parallel, 16-bit reading data received from the SDRAM 20 tothe reading data buffer unit 504.

[0325] 2.2. Operation

[0326] 2.2.1. Read Operation

[0327]FIG. 8 is a timing diagram for signals transmitted between thememory control unit 50 and the SDRAM 20 when the memory control unit 50reads data from the SDRAM 20.

[0328] (Before T61)

[0329] The CPU 30 sends a reading request, and a start row address and astart column address indicating a memory cell from which data readingstarts, to the memory control unit 50.

[0330] Here, it is assumed that a start row address of 0 and a startcolumn address of 0x0A01 are input.

[0331] The control unit 506 receives the reading request from the CPU30.

[0332] The address buffer unit 501 receives and stores therein the startrow address and the start column address.

[0333] The address buffer unit 501 sends the start column address to theoffset control unit 502.

[0334] The offset control unit 502 generates a reading column addressbased on the received start column address.

[0335] Here, the reading column address is 0x0A00.

[0336] The offset value generated by the offset control unit 502 is 1.

[0337] (T61, Between T61 and T62)

[0338] The control unit 506 sends a selection instruction of 1 to theselector 505.

[0339] The selector 505 receives the selection instruction, and connectsthe buses 131 and 531 with the bus 122.

[0340] The address buffer unit 501 outputs a reading row address to thebus 531 in response to an instruction from the control unit 506.

[0341] The control unit 506 holds CKE and DQM high.

[0342] The control unit 506 holds CAS and WE high, and CS and RAS low,to generate an active command.

[0343] (T62, Between T62 and T63)

[0344] At the time T62, the SDRAM 20 receives the active command and thereading row address.

[0345] (T63, Between T63 and T65)

[0346] At the time T63, the control unit 506 holds CS high.

[0347] (T65, Between T65 and T66)

[0348] The control unit 506 sends a selection instruction of 2 to theselector 505.

[0349] The selector 505 receives the selection instruction, and connectsthe buses 131 and 532 with the bus 122.

[0350] The offset control unit 502 outputs the reading column address tothe bus 532 in response to an instruction from the control unit 506.

[0351] The control unit 506 holds DQM low.

[0352] The control unit 506 holds CS and CAS low, and RAS and WE high,to generate a read command.

[0353] (T66, Between T66 and T67)

[0354] At the time T66, the SDRAM 20 receives the read command and thereading column address.

[0355] The control unit 506 maintains control signals as they are.

[0356] (T67)

[0357] The control unit 506 holds CS and CAS high.

[0358] (Between T67 and T69, T69)

[0359] The control unit 506 sends a selection instruction of 4 to theselector 505.

[0360] The selector 505 connects the bus 534 with the bus 122.

[0361] (Between T69 and T71)

[0362] The SDRAM 20 outputs the reading data 311 stored in the memorycell 301 indicated by the reading column address, to the bus 122.

[0363] At the time T70, the reading data buffer unit 504 receives andstores therein the reading data 311.

[0364] (T71, Between T71 and T73)

[0365] The SDRAM 20 outputs the reading data 312 stored in the memorycell 302 to the bus 122.

[0366] At the time T72, the reading data buffer unit 504 receives andstores therein the reading data 312.

[0367] (T73)

[0368] The control unit 506 holds DQM high.

[0369] (Between T73 and T75)

[0370] The SDRAM 20 outputs the reading data 313 stored in the memorycell 303 to the bus 122.

[0371] At the time T74, the reading data buffer unit 504 receives thereading data 313.

[0372] (T75, Between T75 and T77)

[0373] The SDRAM 20 outputs the reading data 314 stored in the memorycell 304 to the bus 122.

[0374] At the time T76, the reading data buffer unit 504 receives thereading data 314.

[0375] (T77, AFTER T77)

[0376] The reading data buffer unit 504 first outputs the reading data312 to the CPU 30, as the reading data 312 has been read from the memorycell 302 which is indicated by an address gained by adding the offsetvalue to a block start address. After this, the reading data buffer unit504 outputs the reading data 313, the reading data 314, and the readingdata 311 to the CPU 30 in the stated order.

[0377] The control unit 506 generates a burst stop command.

[0378] The memory control unit 50 ignores reading data output from theSDRAM 20 after the time T77.

[0379] 2.2.2. Write Operation

[0380]FIG. 9 is a timing diagram for signals transmitted between thememory control unit 50 and the SDRAM 20 when the memory control unit 50writes data into the SDRAM 20.

[0381] (Before T91)

[0382] The CPU 30 outputs, to the memory control unit 50, a writingrequest, a start row address and a start column address indicating amemory cell from which data writing starts, and data to be writtencomposed of the writing data 202, the writing data 203, the writing data204, and the writing data 201.

[0383] The control unit 506 receives the writing request form the CPU30.

[0384] The address buffer unit 501 receives and stores therein the startrow address and the start column address.

[0385] The address buffer unit 501 sends the start column address to theoffset control unit 502.

[0386] The offset control unit 502 generates an offset value and awriting column address based on the start column address.

[0387] Here, the offset value is one, and the writing column address is0x0A03.

[0388] (T91, Between T91 and T92)

[0389] The control unit 506 sends a selection instruction of 1 to theselector 505.

[0390] The selector 505 receives the selection instruction, and connectsthe buses 131 and 531 with the bus 122.

[0391] The address buffer unit 501 outputs the start row address to thebus 531 in response to an instruction from the control unit 506.

[0392] The control unit 506 holds CKE and DQM high.

[0393] The control unit 506 holds CAS and WE high, and CS and RAS low,to generate an active command.

[0394] (T92, Between T92 and T93)

[0395] At the time T92, the SDRAM 20 receives the active command.

[0396] (T93)

[0397] The control unit 506 holds CS high.

[0398] (Between T93 and T95)

[0399] The control unit 506 sends a selection instruction of 2 to theselector 505.

[0400] The selector 505 connects the buses 131 and 532 with the bus 122.

[0401] (T95, Between T95 and T96)

[0402] The offset control unit 502 outputs the writing column address tothe bus 532 in response to an instruction from the control unit 506.

[0403] At the time T95, the control unit 506 holds DQM high.

[0404] At the time T96, the control unit 506 holds CS, CAS and WE low,and RAS high, to generate a write command.

[0405] (T96, Between T96 and T97)

[0406] At the time T96, the SDRAM 20 receives the write command and thewriting column address.

[0407] As DQM is held high at the time T96, the SDRAM 20 does not writedata into the memory cell 304 that is indicated by the writing columnaddress.

[0408] Between the time T96 and the time T97, the control unit 506 sendsa selection instruction of 3 to the selector 505.

[0409] The selector 505 connects the bus 533 with the bus 122.

[0410] (T97)

[0411] The control unit 506 holds CS and CAS high.

[0412] The control unit 506 holds DQM low.

[0413] (Between T97 and T99)

[0414] The writing data buffer unit 503 outputs the writing data 201 tothe bus 533 in response to an instruction from the control unit 506.

[0415] At the time T98, the SDRAM 20 writes the writing data 201 intothe memory cell 301, which is judged as having an address next to theaddress of the memory cell 304 in a wraparound method.

[0416] (T99, Between T99 and T101)

[0417] The writing data buffer unit 503 outputs the writing data 202 tothe bus 533 in response to an instruction from the control unit 506.

[0418] At the time T100, the SDRAM 20 writes the writing data 202 to thememory cell 302 which has an address next to that of the memory cell301.

[0419] (T101, Between T101 and T103)

[0420] The writing data buffer unit 503 outputs the writing data 203 tothe bus 533 in response to an instruction from the control unit 506.

[0421] At the time T102, the SDRAM 20 writes the writing data 203 to thememory cell 303 which has an address next to that of the memory cell302.

[0422] (T103, Between T103 and T105)

[0423] The writing data buffer unit 503 outputs the writing data 204 tothe bus 533 in response to an instruction from the control unit 506.

[0424] At the time T104, the SDRAM 20 writes the writing data 204 to thememory cell 304 which has an address next to that of the memory cell303.

[0425] (T105)

[0426] The control unit 506 holds DQM high.

[0427] The control unit 506 holds CS and WE low, and RAS and CAS high,to generate a burst stop command.

[0428] (Between T105 and T107)

[0429] At the time T106, the SDRAM 20 receives the burst stop command.

[0430] 3. Third Embodiment

[0431] 3.1. Construction

[0432]FIG. 10 illustrates a construction of an information processingapparatus 3, which includes a memory unit 60 relating to a thirdembodiment of a memory of the present invention.

[0433] The memory unit 60 is electrically connected to a memory controlunit 70 by a bus as shown in FIG. 10.

[0434] The memory unit 60 has a memory area shown in FIG. 3.

[0435] The CPU 30 requests the memory control unit 70 to write thewriting data 202, the writing data 203, the writing data 204, and thewriting data 201 (shown in FIG. 2) into the memory cells 302, 303, 304and 301 respectively, in the stated order.

[0436] In response to a request from the CPU 30, the memory control unit70 respectively writes the writing data 202, the writing data 203, thewriting data 204, and the writing data 201 into the memory cells 302,303, 304, and 301 in the memory unit 60, in the stated order.

[0437] Also, the CPU 30 requests the memory control unit 70 to read datastored in the memory cells 302, 303, 304, and 301.

[0438] In response to a reading request from the CPU 30, the memorycontrol unit 70 reads data from the memory cells 302, 303, 304, and 301,and sends the read data to the CPU 30.

[0439] Specifically speaking, the memory unit 60 is an SDRAM, and thememory control unit 70 is an LSI formed by a logic circuit or the like.

[0440] In the memory unit 60, a burst length is set to four.

[0441]FIG. 11 is a block diagram illustrating a construction of thememory unit 60.

[0442] As shown in FIG. 11, DQ0 is connected to A0, and DQ1 is connectedto A1. DQ2 to DQ13 are connected to A2 to A13 respectively. D14 isconnected to RAS, and D15 is connected to CAS.

[0443] (Address Buffer 601)

[0444] An address buffer 601 receives a latch instruction and addressinformation from a timing generator 606 (mentioned later).

[0445] Address information is one of a row address and a column address.

[0446] The address buffer 601 latches signals input to DQ0 to DQ15, onreception of a latch instruction from the timing generator 606.

[0447] When address information is a row address, the address buffer 601latches the row address and sends the latched row address to a memorycell array 605 (mentioned later). When address information is a columnaddress, the address buffer 601 latches the column address and sends thelatched column address to an address addition unit 602 (mentionedlater).

[0448] (Address Addition Unit 602)

[0449] The address addition unit 602 receives a column address from theaddress buffer 601, and stores it as an input/output address.

[0450] On receiving an increment instruction from the timing generator606, the address addition unit 602 increments the input/output addressstored therein, with reference to a burst length stored in the timinggenerator 606, using a wraparound method.

[0451] The address addition unit 602 outputs the incrementedinput/output address to the memory cell array 605.

[0452] (Refresh Counter 603)

[0453] A refresh counter 603 generates a row address of a memory cell tobe refreshed, to perform a refresh operation. After this, the refreshcounter 603 informs the memory cell array 605 of the generated rowaddress.

[0454] (Io Buffer 604)

[0455] An IO buffer 604 receives a latch instruction and an operationsignal from the timing generator 606.

[0456] An operation signal indicates one of a reading operation and awriting operation.

[0457] The IO buffer 604 performs the following operations when itreceives a latch instruction. If the IO buffer 604 receives an operationsignal indicating a reading operation, the IO buffer 604 latches signalsoutput from the memory cell array 605, and sends them to DQ0 to DQ15. Ifthe IO buffer 604 receives an operation signal indicating a writingoperation, the IO buffer 604 latches signals input to from DQ0 to DQ15,and sends them to the memory cell array 605.

[0458] (Memory Cell Array 605)

[0459]FIG. 12 briefly illustrates a construction of the memory cellarray 605.

[0460] A memory cell in the memory cell array 605 has the same circuitconstruction as a memory cell in a general-purpose DRAM. That is to say,a memory cell is constituted by one transistor and one condenser.

[0461] On receiving a row address from the address buffer 601, a rowdecoder of the memory cell array 605 reads the row address, and selectsa word line corresponding to the row address. On receiving a columnaddress from the address addition unit 602, a column decoder of thememory cell array 605 reads the column address, and selects a digit linecorresponding to the column address. Thus, an address is decoded.

[0462] When the memory cell array 605 receives a writing instructionfrom the timing generator 606, the memory cell array 605 writes datalatched by the IO buffer 604 into an address that has been decoded. Whenreceiving a reading instruction, the memory cell array 605 outputs datastored in an address that has been decoded to the IO buffer 604.

[0463] The memory cell array 605 includes the memory cells 301, 302, 303and 304.

[0464] (Timing Generator 606)

[0465] The timing generator 606 receives control signals including CLK,CKE, CS, RAS, CAS, and WE from the CPU 30. The timing generator 606gives an instruction to the address buffer 601, the address additionunit 602, the refresh counter 603, the IO buffer 604, and the memorycell array 605, based on the above-mentioned control signals.

[0466] 3.2. Operation

[0467] 3.2.1. Write Operation

[0468]FIG. 13 is a timing diagram for signals transmitted between thememory control unit 70 and the memory unit 60 when the memory controlunit 70 writes data into the memory unit 60.

[0469] At the time T201, the memory control unit 70 outputs an activecommand and a row address.

[0470] The timing generator 606 outputs a latch instruction and addressinformation indicating a row address to the address buffer 601.

[0471] The address buffer 601 latches the row address, and outputs thelatched row address to the memory cell array 605.

[0472] At the time T202, the memory control unit 70 outputs a writecommand and a column address.

[0473] The timing generator 606 outputs a latch instruction and addressinformation indicating a column address to the address buffer 601.

[0474] The address buffer 601 latches the column address, and outputsthe latched column address to the address addition unit 602.

[0475] The address addition unit 602 stores the column address as aninput/output address, and outputs the input/output address to the memorycell array 605.

[0476] Here, it is assumed that the input/output address is 0x0A01, i.e.the column address of the memory cell 302.

[0477] At the time T203, the memory control unit 70 outputs the writingdata 202.

[0478] At this point, the timing generator 606 does not send anincrement instruction to the address addition unit 602.

[0479] The timing generator 606 outputs a latch instruction and anoperation signal indicating a writing operation, to the IO buffer 604.

[0480] The IO buffer 604 latches signals input to from DQ0 to DQ15 inaccordance with the latch instruction, and outputs the latched signalsto the memory cell array 605.

[0481] The timing generator 606 outputs a writing instruction to thememory cell array 605.

[0482] The memory cell array 605 writes the writing data 202 into thememory cell 302.

[0483] When the writing data 202 has been written, the timing generator606 sends an increment instruction to the address addition unit 602.

[0484] The address addition unit 602 increments the input/output addressstored therein, and outputs 0x0A02, that is to say, the column addressof the memory cell 303, to the memory cell array 605.

[0485] At the time T204, the memory control unit 70 outputs the writingdata 203.

[0486] The timing-generator 606 outputs a latch instruction and anoperation signal indicating a writing operation to the IO buffer 604.

[0487] The IO buffer 604 latches signals input to from DQ0 to DQ15 inaccordance with the latch instruction, and sends the latched signals tothe memory cell array 605.

[0488] The timing generator 606 outputs a writing instruction to thememory cell array 605.

[0489] The memory cell array 605 writes the writing data 203 into thememory cell 303 indicated by the input/output address.

[0490] When the writing data 203 has been written, the timing generator606 sends an increment instruction to the address addition unit 602.

[0491] The address addition unit 602 increments the input/output addressstored therein, and outputs 0x0A03, that is to say, the column addressof the memory cell 304, to the memory cell array 605.

[0492] At the time T205, the memory control unit 70 outputs the writingdata 204.

[0493] The timing generator 606 outputs a latch instruction and anoperation signal indicating a writing operation to the IO buffer 604.

[0494] The IO buffer 604 latches signals input to from DQ0 to DQ15 inaccordance with the latch instruction, and outputs the latched signalsto the memory cell array 605.

[0495] The timing generator 606 outputs a writing instruction to thememory cell array 605.

[0496] The memory cell array 605 writes the writing data 204 into thememory cell 304 indicated by the input/output address.

[0497] When the writing data 204 has been written, the timing generator606 sends an increment instruction to the address addition unit 602.

[0498] The address addition unit 602 increments the input/output addressstored therein using a wraparound method, and outputs 0x0A00, that is tosay, the column address of the memory cell 301, to the memory cell array605.

[0499] At the time T206, the memory control unit 70 outputs the writingdata 201.

[0500] The timing generator 606 outputs a latch instruction and anoperation signal indicating a writing operation to the IO buffer 604.

[0501] The IO buffer 604 latches signals input to from DQ0 to DQ15 inaccordance with the latch instruction, and outputs the latched signalsto the memory cell array 605.

[0502] The timing generator 606 outputs a writing instruction to thememory cell array 605.

[0503] The memory cell array 605 writes the writing data 201 into thememory cell 301 indicated by the input/output address.

[0504] At the time 207, the memory control unit 70 outputs a burst stopcommand. Thus, a data writing operation is ended.

[0505] 3.2.2. Read Operation

[0506] The memory cells 301, 302, 303 and 304 respectively store thereading data 311, the reading data 312, the reading data 313 and thereading data 314 as shown in FIG. 2.

[0507]FIG. 14 is a timing diagram for signals transmitted between thememory control unit 70 and the memory unit 60 when the memory controlunit 70 reads data from the memory unit 60.

[0508] At the time T251, the memory control unit 70 outputs an activecommand and a row address.

[0509] The timing generator 606 outputs a latch instruction and addressinformation indicating a row address, to the address buffer 601.

[0510] The address buffer 601 latches the row address, and outputs thelatched row address to the memory cell array 605.

[0511] At the time T252, the memory control unit 70 outputs a readcommand and a column address.

[0512] Receiving the read command and the column address, the timinggenerator 606 outputs a latch instruction and address informationindicating a column address to the address buffer 601.

[0513] The address buffer 601 latches the column address, and outputsthe latched column address to the address addition unit 602.

[0514] The address addition unit 602 stores the column address thereinas an input/output address, and outputs the input/output address to thememory cell array 605.

[0515] Here, it is assumed that the input/output address is 0x0A01, i.e.the column address of the memory cell 302.

[0516] The timing generator 606 outputs a reading instruction to thememory cell array 605.

[0517] The memory cell array 605 outputs the reading data 312 stored inthe memory cell 302 to the IO buffer 604 during two clocks (CASLatency=2) from the time T252 to the time T253.

[0518] At the time T253, the timing generator 606 outputs a latchinstruction and an operation signal indicating a reading operation tothe IO buffer 604.

[0519] The IO buffer 604 latches signals indicating the reading data 312output from the memory cell array 605 in accordance with the latchinstruction, and outputs the latched signals to from DQ0 to DQ15.

[0520] The memory control unit 70 receives the reading data 312 that hasbeen output to from DQ0 to DQ15.

[0521] The timing generator 606 outputs an increment instruction to theaddress addition unit 602.

[0522] The address addition unit 602 increments the input/output addressstored therein, and outputs 0x0A02, that is to say, the column addressof the memory cell 303 to the memory cell array 605.

[0523] The timing generator 606 outputs a reading instruction to thememory cell array 605.

[0524] The memory cell array 605 outputs the reading data 313 stored inthe memory cell 303 to the IO buffer 604.

[0525] At the time T254, the timing generator 606 outputs a latchinstruction and an operation signal indicating a reading operation tothe IO buffer 604.

[0526] The IO buffer 604 latches signals indicating the reading data 313output from the memory cell array 605 in accordance with the latchinstruction, and outputs the latched signals to from DQ0 to DQ15.

[0527] The memory control unit 70 receives the reading data 313 that hasbeen output to from DQ0 to DQ15.

[0528] The timing generator 606 outputs an increment instruction to theaddress addition unit 602.

[0529] The address addition unit 602 increments the input/output addressstored therein, and outputs 0x0A03, that is to say, the column addressof the memory cell 304 to the memory cell array 605.

[0530] The timing generator 606 outputs a reading instruction to thememory cell array 605.

[0531] The memory cell array 605 outputs the reading data 314 stored inthe memory cell 304 to the IO buffer 604.

[0532] At the time T255, the memory control unit 70 sends a burst stopcommand.

[0533] The timing generator 606 outputs a latch instruction and anoperation signal indicating a reading operation to the IO buffer 604.

[0534] The IO buffer 604 latches signals indicating the reading data 314output from the memory cell array 605 in accordance with the latchinstruction, and outputs the latched signals to from DQ0 to DQ15.

[0535] The memory control unit 70 receives the reading data 314 that hasbeen output to DQ0 to DQ15.

[0536] The timing generator 606 outputs an increment instruction to theaddress addition unit 602.

[0537] The address addition unit 602 increments the input/output addressstored therein using a wraparound method, and outputs 0x0A00, that is tosay, the column address of the memory cell 301 to the memory cell array605.

[0538] The timing generator 606 outputs a reading instruction to thememory cell array 605.

[0539] The memory cell array 605 outputs the reading data 311 stored inthe memory cell 301 to the IO buffer 604.

[0540] At the time T256, the timing generator 606 outputs a latchinstruction and an operation signal indicating a reading operation tothe IO buffer 604.

[0541] The IO buffer 604 latches signals indicating the reading data 311output from the memory cell array 605 in accordance with the latchinstruction, and outputs the latched signals to from DQ0 to DQ15.

[0542] The memory control unit 70 receives the reading data 311 that hasbeen output to from DQ0 to DQ15.

[0543] 4. Other Modifications

[0544] The present invention is described with reference to theabove-mentioned embodiments, but not limited thereto.

[0545] The present invention includes the following modifications.

[0546] (1) The clock generation unit 103 in the first embodiment may beomitted. In this case, the CPU 30 supplies CLK to the memory controlunit 10 and the SDRAM 20.

[0547] (2) According to the first embodiment, the CPU 30 sends theentire writing data corresponding to one memory block to the memorycontrol unit 10 before the memory control unit 10 starts a writeoperation. Alternatively, however, the CPU 30 may send writing datacorresponding to each memory cell by the time the memory control unit 10outputs a signal for writing the data corresponding to the memory cellto the SDRAM 20.

[0548] (3) According to the second embodiment, the memory control unit50 receives the entire reading data corresponding to one memory blockfrom the SDRAM 20 before sending reading data to the CPU 30. However,the memory control unit 50 may start sending data read from the SDRAM 20with reading data corresponding to a start column address, beforereceiving the entire reading data corresponding to one memory block.

[0549] (4) The present invention may be an operation having the stepsdescribed in the embodiments, a computer program that performs theoperation using a computer, or digital signals formed by the computerprogram.

[0550] The present invention may be the computer program or the digitalsignals in a state of being stored in a computer readable storagemedium, for example, a flexible disk, a hard disk, a CD-ROM, an MO, aDVD, a DVD-ROM, a DVD-RAM, Blue-Ray Disc (BD) or a semiconductor memory.The present invention may be the computer program or the digital signalsstored in the above-mentioned storage media.

[0551] Alternatively, the present invention may be transmission of thecomputer program or the digital signals via a network, such as anelectronic communication network, a wireless or a fixed-linecommunication network, and the Internet.

[0552] The present invention may be a computer system including amicroprocessor and a memory. The memory stores the above-mentionedcomputer program, and the microprocessor performs an operationcorresponding to the computer program.

[0553] The present invention may be realized in the following manner.The above-mentioned computer program or digital signals in a state ofbeing stored in the above-mentioned storage media is transferred, or thecomputer program or the digital signals are transmitted via theabove-mentioned networks, so as that a different computer systemexecutes the computer program or the digital signals.

[0554] Although the present invention has been fully described by way ofexamples with reference to the accompanying drawings, it is to be notedthat various changes and modifications will be apparent to those skilledin the art.

[0555] Therefore, unless otherwise such changes and modifications departfrom the scope of the present invention, they should be construed asbeing included therein.

What is claimed is:
 1. An information processing apparatus comprising: amemory unit that has a predetermined burst length and is operable totransfer block data, using a wrap around method, to/from a memory blockthat is constituted by a plurality of consecutive memory cells in thememory unit and has a length equal to the predetermined burst length;and a memory control unit that is connected to the memory unit by a busused for both address transfer and data transfer, wherein the memorycontrol unit includes an output subunit operable to output a firstcommand and a second command, when the transfer of the block datato/from the memory block starts with transfer of data to/from anintermediate memory cell in the memory block, the intermediate memorycell being a memory cell other than an initial memory cell in the memoryblock, the first command instructing the memory unit to transfer datato/from each of the plurality of memory cells in the memory block,except for a memory cell directly before the intermediate memory cell,the second command being output when a predetermined time has elapsedsince the output of the first command, and instructing the memory unitto transfer data to/from the memory cell directly before theintermediate memory cell in the memory block, and the memory unittransfers the block data in accordance with the first command and thesecond command.
 2. The information processing apparatus of claim 1,wherein the memory unit is an SDRAM.
 3. The information processingapparatus of claim 1, wherein the first command includes a writinginstruction and an address indicating the memory cell directly beforethe intermediate memory cell, the second command includes a writinginstruction and an address indicating a memory cell two memory cellsbefore the intermediate memory cell.
 4. The information processingapparatus of claim 1, wherein the first command includes a readinginstruction and an address indicating the intermediate memory cell, thesecond command includes a reading instruction and an address indicatingthe memory cell directly before the intermediate memory cell.
 5. Aninformation processing apparatus comprising: a memory unit that has aburst length larger than a block length of a memory block and isoperable to transfer block data to/from the memory block constituted bya plurality of consecutive memory cells in the memory unit; a memorycontrol unit that is connected to the memory unit by a bus used for bothaddress transfer and data transfer; a cache unit operable to request thememory control unit to transfer the block data to/from the memory unit;a writing unit operable to (i) receive, from the cache unit, an addressindicating an intermediate memory cell in the memory block, the blockdata, and a writing request, the intermediate memory cell being a memorycell other than an initial memory cell in the memory block, and (ii)store data into each of the plurality of memory cells in the memoryblock in the memory unit in an order of from the initial memory cell toa final memory cell in the memory block; and a reading unit operable to(a) receive, from the cache unit, the address indicating theintermediate memory cell in the memory block, and a reading request, (b)read data from each of the plurality of memory cells in the memory blockin the memory unit in an order of from the initial memory cell to thefinal memory cell, and (c) send the read data to the cache unit, using awraparound method, starting with data read from the intermediate memorycell and ending with data read from a memory cell directly before theintermediate memory cell.
 6. The information processing apparatus ofclaim 5, wherein the memory unit is an SDRAM.
 7. A memory operable tostore data in accordance with signals input thereto, the signalsincluding a control signal such as a clock, an address signal, and adata signal, the memory comprising: a transmission unit operable totransmit the signals; a detection unit operable to detect an edge of theclock; a memory cell group that is constituted by a plurality of memorycells each of which has an assigned address; an address storing unitoperable to (i) retrieve an address signal when the detection unitdetects an edge of the clock at a predetermined timing, and (ii) storetherein the retrieved address signal as a writing address; an addressaddition unit operable to increment the writing address, after an edgeis detected subsequent to the detection of the edge at the predeterminedtiming, but before a next edge is detected; a data storing unit operableto retrieve a data signal every time the detection unit detects an edgeof the clock, after the detection unit detects the edge at thepredetermined timing; and a control unit operable to perform control sothat, every time the data storing unit retrieves a data signal, theretrieved data signal is written into a memory cell indicated by thewriting address stored in the address storing unit.
 8. The memory ofclaim 7, wherein the transmission unit includes: one signal input/outputterminal for two of the address signal, the data signal, and the controlsignal, one of the two signals being input to the signal input/outputterminal at a time; and a signal line which is connected to two unitsselected from (i) the address storing unit that stores the writingaddress indicating the memory cell to which the data signal is to bewritten, (ii) the data storing unit that stores the data signal that isto be written to the memory cell, and (iii) the control unit thatcontrols the writing of the data signal, so as that the selected twounits correspond to the two signals input to the signal input/outputterminal.
 9. The memory of claim 7, that is formed by an SDRAM.
 10. Aninformation processing method for transferring data to/from a memory bymeans of a bus used for both address transfer and data transfer, thememory operating in accordance with a command, having a predeterminedburst length, and transferring block data, by using a wraparound method,to/from a memory block that is constituted by a plurality of memorycells in the memory and has a length equal to the predetermined burstlength, the information processing method comprising: a first outputstep of, when the transfer of the block data to/from the memory blockstarts with transfer of data to/from an intermediate memory cell in thememory block, the intermediate memory cell being a memory cell otherthan an initial memory cell in the memory block, outputting a firstcommand to instruct the memory to transfer data to/from each of theplurality of memory cells in the memory block, except for a memory celldirectly before the intermediate memory cell; and a second output stepof, when a predetermined time has elapsed since the output of the firstcommand, outputting a second command to instruct the memory to transferdata to/from the memory cell directly before the intermediate memorycell in the memory block.
 11. A program used in an informationprocessing apparatus that transfers data to/from a memory by means of abus used for both address transfer and data transfer, the memoryoperating in accordance with a command, having a predetermined burstlength, and transfer block data, by using a wraparound method, to/from amemory block that is constituted by a plurality of memory cells in thememory and has a length equal to the predetermined burst length, theprogram comprising: a first output step of, when the transfer of theblock data to/from the memory block starts with transfer of data to/froman intermediate memory cell in the memory block, the intermediate memorycell being a memory cell other than an initial memory cell in the memoryblock, outputting a first command to instruct the memory to transferdata to/from each of the plurality of memory cells in the memory block,except for a memory cell directly before the intermediate memory cell;and a second output step of, when a predetermined time has elapsed sincethe output of the first command, outputting a second command to instructthe memory to transfer data to/from the memory cell directly before theintermediate memory cell in the memory block.